HID - Digital Sensor Module
Communication and Programming
Application Note HID/HCM-G - Digital Sensor Module Communication And Programming - Rev 07 Page 3 of 16
Output settling time Tset
VDD = 5V
100 pF capacitive load, full
operating Ta range , VDD = 5V 500 ns
Output settling time Tset
VDD = 3V
100 pF capacitive load, full
operating Ta range , VDD = 3V 150 ns
Output settling time TsetRC
VDD = 5V
220 Ohm in series with 47nF
load on the wire, full Ta
operating range , VDD = 5V
20 50 us
Output settling time TsetRC
VDD = 3V
220 Ohm in series with 47nF
load on the wire, full Ta
operating range , VDD = 3V
500 ns
Parameter Symbol Test Conditions Min Typ Max Units
SMBus compatible 2-wire interface
2
Input high voltage VIH 1.8 2 2.2 V
Input high voltage VIH 1.6 2 2.4 V
Input high voltage VIH(Ta,V) Over temperature and supply 1.6 2.4 V
Input high voltage VIH(Ta,V) Over temperature and supply 1.2 2 2.8 V
Input low voltage VIL 0.7 1.0 1.3 V
Input low voltage VIL(Ta,V) Over temperature and supply 0.5 1.5 V
Output low voltage VOL
SDA pin in open drain mode,
over temperature and supply,
Isink = 2mA
0.2 V
SCL leakage ISCL,leak VSCL=4V, Ta=+85°C 30 uA
SDA leakage ISDA,leak VSDA=4V, Ta=+85°C 0.3 uA
SCL capacitance CSCL 10 pF
SDA capacitance CSDA 10 pF
Slave address SA Factory default 5Ah hex
SMBus Request tREQ SCL low 1.024 ms
Timeout, low Timeout,L SCL low 30 ms
Timeout, high Timeout,H SCL high 50 us
Acknowledge setup time Tsuac(MD) 8-th SCL falling edge, Master 0.5 1.5 us
Acknowledge hold time Thdac(MD) 9-th SCL falling edge, Master 1.5 2.5 us
Acknowledge setup time Tsuac(SD) 8-th SCL falling edge, Slave 2.5 us
Acknowledge hold time Thdac(SD) 9-th SCL falling edge, Slave 1.5 us
EEPROM
Data retention Ta = +85°C 10 years
Erase/write cycles Ta = +25°C 100,000 Times
Erase/write cycles Ta = +125°C 10,000 Times
Erase cell time Terase 5 ms
Write cell time Twrite 5 ms
CN
EN